? semiconductor components industries, llc, 2013 august, 2013 ? rev. 13 1 publication order number: ntd2955/d ntd2955, nvd2955 power mosfet ? 60 v, ? 12 a, p ? channel dpak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. designed for low ? voltage, high ? speed switching applications in power supplies, converters, and power motor controls. these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer an additional safety margin against unexpected voltage transients. features ? avalanche energy specified ? i dss and v ds(on) specified at elevated temperature ? designed for low ? voltage, high ? speed switching applications and to withstand high energy in the avalanche and commutation modes ? nvd prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these devices are pb ? free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss ? 60 vdc gate ? to ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gsm 20 25 vdc vpk drain current drain current ? continuous @ t a = 25 c drain current ? single pulse (t p 10 ms) i d i dm ? 12 ? 18 adc apk total power dissipation @ t a = 25 c p d 55 w operating and storage temperature range t j , t stg ? 55 to 175 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, peak i l = 12 apk, l = 3.0 mh, r g = 25 ) e as 216 mj thermal resistance ? junction ? to ? case ? junction ? to ? ambient (note 1) ? junction ? to ? ambient (note 2) r jc r ja r ja 2.73 71.4 100 c/w maximum lead temperature for soldering purposes, 1/8 in. from case for 10 seconds t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. when surface mounted to an fr4 board using 1 in pad size (cu area = 1.127 in 2 ). 2. when surface mounted to an fr4 board using the minimum recommended pad size (cu area = 0.412 in 2 ). d s g p ? channel http://onsemi.com ? 60 v 155 m @ ? 10 v, 6 a r ds(on) typ ? 12 a i d max v (br)dss y = year ww = work week g = pb ? free package 1 gate 3 source 2 drain 4 drain dpak case 369c style 2 marking diagrams 1 2 3 4 dpak ? 3 case 369d style 2 1 2 3 4 yww nt 2955g see detailed ordering and shipping information in the package dimensions sect ion on page 6 of this data sheet. ordering information 1 gate 3 source 2 drain 4 drain yww nt 2955g 1 gate 3 source 2 drain 4 drain yww ntp 2955g
ntd2955, nvd2955 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (note 3) (v gs = 0 vdc, i d = ? 0.25 ma) (positive temperature coefficient) v (br)dss ? 60 ? ? 67 ? ? vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = ? 60 vdc, t j = 25 c) (v gs = 0 vdc, v ds = ? 60 vdc, t j = 150 c) i dss ? ? ? ? ? 10 ? 100 adc gate ? body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? ? 100 nadc on characteristics (note 3) gate threshold voltage (v ds = v gs , i d = ? 250 adc) (negative temperature coefficient) v gs(th) ? 2.0 ? ? 2.8 4.5 ? 4.0 ? vdc mv/ c static drain ? source on ? state resistance (v gs = ? 10 vdc, i d = ? 6.0 adc) r ds(on) ? 0.155 0.180 drain ? to ? source on ? voltage (v gs = ? 10 vdc, i d = ? 12 adc) (v gs = ? 10 vdc, i d = ? 6.0 adc, t j = 150 c) v ds(on) ? 1.86 ? ? 2.6 ? 2.0 vdc forward transconductance (v ds = 10 vdc, i d = 6.0 adc) gfs 8.0 ? mhos dynamic characteristics input capacitance (v ds = ? 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 500 750 pf output capacitance c oss ? 150 250 reverse transfer capacitance c rss ? 50 100 switching characteristics (notes 3 and 4) turn ? on delay time (v dd = ? 30 vdc, i d = ? 12 a, v gs = ? 10 v, r g = 9.1 ) t d(on) ? 10 20 ns rise time t r ? 45 85 turn ? off delay time t d(off) ? 26 40 fall time t f ? 48 90 gate charge (v ds = ? 48 vdc, v gs = ? 10 vdc, i d = ? 12 a) q t ? 15 30 nc q gs ? 4.0 ? q gd ? 7.0 ? drain ? source diode characteristics (note 3) diode forward on ? voltage (i s = 12 adc, v gs = 0 v) (i s = 12 adc, v gs = 0 v, t j = 150 c) v sd ? ? ? 1.6 ? 1.3 ? 2.5 ? vdc reverse recovery time (i s = 12 a, di s /dt = 100 a/ s ,v gs = 0 v) t rr ? 50 ns t a ? 40 ? t b ? 10 ? reverse recovery stored charge q rr ? 0.10 ? c 3. indicates pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature.
ntd2955, nvd2955 http://onsemi.com 3 typical performance curves (t j = 25 c unless otherwise noted) figure 1. on ? region characteristics figure 2. transfer characteristics figure 3. on ? resistance versus drain current and temperature figure 4. on ? resistance versus drain current and gate voltage figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current versus voltage 012345 0 15 25 ? v ds , drain ? to ? source voltage (volts) 24 6 810 0 10 18 24 ? v gs , gate ? to ? source voltage (volts) t j = 25 c v ds ? 10 v t j = -55 c 25 c 125 c v gs = -10 v -9 v -8 v -6 v -5 v -7 v 5 10 20 3579 4 12 22 678910 16 6 03 6 15 24 0 0.10 0.20 0.30 0 6 21 24 0.050 0.075 0.200 0.250 ? i d , drain current (amps) - i d , drain current (amps) t j = 25 c v gs = ? 10 v t j = 125 c 25 c -55 c 12 21 3 12 15 0.05 0.15 0.25 0.100 0.225 0.125 v gs = ? 10 v - 15 v 18 9 0.35 0.40 0.175 918 0.150 -50 0.6 0.8 1.2 1.6 520 5060 1 100 1000 t j , junction temperature ( c) ? v ds , drain ? to ? source voltage (volts) -25 0 25 50 75 100 125 150 v gs = 0 v v gs = ? 10 v i d = ? 6 a 15 30 40 1.0 1.4 t j = 125 c 175 0.4 0.2 0 1.8 2.0 100 c -6.5 v -5.5 v -9.5 v 8 2 20 14 0.45 0.50 10 10 25 55 35 45 ? i d, drain current (a) ? i d, drain current (a) r ds(on), drain ? to ? source resistance ( ) r ds(on), drain ? to ? source resistance ( ) r ds(on), drain ? to ? source resistance (normalized) ? i dss , leakage (na)
ntd2955, nvd2955 http://onsemi.com 4 0.1 1 10 100 0.1 1 10 100 figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( ) 1 10 100 t, time (ns) v dd = ? 30 v i d = ? 12 a v gs = ? 10 v t j = 25 c t f t d(off) 0 q t , total gate charge (nc) 2468 i d = 12 a t j = 25 c v gs 1000 100 10 1 15 10 0 2.5 5 60 50 40 30 0 v ds 14 q t q gs q gd 16 10 12 t d(on) t r 12.5 7.5 20 0 0.25 0.75 1.75 ? v sd , source ? to ? drain voltage (v) v gs = 0 v t j = 25 c 0 10 15 5 0.5 1 1.25 1.5 10 10 0 10 15 25 gate ? to ? source or drain ? to ? source voltage (v) c, capacitance (pf) -v gs -v ds t j = 25 c v ds = 0 v v gs = 0 v 1000 800 600 400 200 0 20 c iss c oss c rss 55 c iss c rss 1200 figure 10. diode forward voltage versus current figure 11. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) v gs = ? 15 v single pulse t c = 25 c dc 100 s 1 ms 10 ms r ds(on) limit thermal limit package limit figure 12. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b i d , drain current (amps) ? v gs , gate ? to ? source voltage (v) ? i s , source current (amps) ? v ds , drain ? to ? source voltage (v)
ntd2955, nvd2955 http://onsemi.com 5 figure 13. thermal response t, time (s) r(t), normalized effective transient thermal resistance r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0 0.1 0.01 0.2 d = 0.5 0.05 0.01 single pulse 0.1 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.02
ntd2955, nvd2955 http://onsemi.com 6 ordering information device package shipping ? ntd2955g dpak (pb ? free) 75 units / rail ntd2955 ? 1g ipak (pb ? free) 75 units / rail ntd2955t4g dpak (pb ? free) 2500 / tape & reel nvd2955t4g* dpak (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nvd prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable.
ntd2955, nvd2955 http://onsemi.com 7 package dimensions dpak (single gauge) case 369c issue d style 2: pin 1. gate 2. drain 3. source 4. drain b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw
ntd2955, nvd2955 http://onsemi.com 8 package dimensions ipak case 369d issue c style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ntd2955/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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